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standard power data sheet rev 1.0, 2012-09-01 ITS4100S-SJ-N smart high-side nm os-power switch
pg-dso-8 data sheet 2 rev 1.0, 2012-09-01 smart high-side nm os-power switch ITS4100S-SJ-N type package marking ITS4100S-SJ-N pg-dso-8 i100sn 1overview features ? cmos compatible input ? switching all types of resistive, inductive and capacitive loads ? fast demagnetization of inductive loads ? very low standby current ? optimized electromagnet ic compatibility (emc) ? overload protection ? current limitation ? short circuit protection ? thermal shutdown with restart ? overvoltage protection (including load dump) ? reverse battery protecti on with external resistor ? loss of gnd and loss of vbb protection ? electrostatic dischar ge protection (esd) ? green product (rohs compliant) ITS4100S-SJ-N is not qualified and manufactured according to the requirements of infineon technologies with regards to automotive and/or transportation applications. description the ITS4100S-SJ-N is a protected single channel smar t high-side nmos-power switch in a pg-dso-8 package with charge pump and cmos compatible input. the devi ce is monolithically integrated in smart technology. product summary overvoltage protection v sazmin = 41v operating voltage range: 5v < v s < 34v on-state resistance r dson = typ 70m ? nominal load current i lnom = 2a operating temperature range: t j = -40c to 125c standby current: i sstb = 15a application ? all types of resistive, in ductive and capacitive loads ? power switch for 12v and 24v dc applications with cmos compatib le control interface ? driver for electromagnetic relays ? power managment for high-side-switching with low current cons umption in off-mode
data sheet 3 rev 1.0, 2012-09-01 ITS4100S-SJ-N block diagram and terms 2 block diagram and terms figure 1 block diagram figure 2 terms - parameter definition 3 ITS4100S-SJ-N gate control circuit 7 temperature sensor in out vs 6 5 8 bias supervision overvoltage protection esd protection logic current limiter 2 1 gnd nc 4 v st v out v s i s i l r l v fds gnd voltage- and current-definitions: switching times and slew rate definitions: off off on v ds v out 90% 0 +v s 10% t off t i l t 0 t on sr on 30% sr off 70% 40% t 3 ITS4100S-SJ-N 4 gate control circuit 7 temperature sensor in out vs 6 5 8 bias supervision overvoltage protection esd protection logic current limiter 2 1 nc gnd v in i in i out v in l h
data sheet 4 rev 1.0, 2012-09-01 ITS4100S-SJ-N pin configuration 3 pin configuration 3.1 pin assignment figure 3 pin configuration top view, pg-dso-8 3.2 pin definitions and functions pin symbol function 1 gnd logic ground 2 in input, controles the power switch; the powerswitch is on when high 3 out output to the load 4 nc not connected 5, 6, 7, 8 vs supply voltage (design the wiring for the maximum short circuit current and also for low thermal resistance) vs in nc gnd vs out vs vs 8 5 6 7 1 4 3 2 p-dso-8
data sheet 5 rev 1.0, 2012-09-01 ITS4100S-SJ-N general product characteristics 4 general product characteristics 4.1 absolute maximum ratings note: exposure to absolute maximum rating conditions for extended periods may affect device reliability. integrated protection functions are desi gned to prevent ic destruction unde r fault conditions described in the data sheet. fault conditions are considered as ?outside? the normal operating range. protection functions are neither designed for contin uous nor repetitive operation. table 1 absolute maximum ratings 1) at t j = 25c unless otherwise specified. currents flowing into the device unless otherwise specified in chapter ?block diagram and terms? 1) not subject to production test, specified by design parameter symbol values unit note / test condition number min. typ. max. supply voltage vs voltage v s 40 v 4.1.1 voltage for short circuit protection v ssc v s v-40c< t j < 150c 4.1.2 output stage out output current; (short circuit current see electrical characteristics) i out self limited a 4.1.3 input in voltage v in -10 16 v 4.1.4 current i in -5 5 ma 4.1.5 temperatures junction temperature t j -40 125 c 4.1.6 storage temperature t stg -55 125 c 4.1.7 power dissipation ta = 25 c 2) 2) device on 50mm*50mm*1.5mm epoxy pcb fr4 with 6 cm2 (one layer, 70mm thick) copper area for vbb connection. pcb is vertical without blown air p tot 1.5 w 4.1.8 inductive load switch-off energy dissipation tj = 125 c; v s =13.5v; i l = 1a 3) 3) not subject to production test, specified by design e as 870 mj single pulse 4.1.9 esd susceptibility esd susceptibility (input pin) v esd -1 1 kv hbm 4) 4) esd susceptibility hbm according to eia/jesd 22-a 114. 4.1.10 esd susceptibility (all other pins) v esd -5 5 kv hbm 4) 4.1.11
data sheet 6 rev 1.0, 2012-09-01 ITS4100S-SJ-N general product characteristics 4.2 functional range note: within the functional range the ic operates as de scribed in the circuit description. the electrical characteristics are specifi ed within the conditions given in the re lated electrical ch aracteristics table. 4.3 thermal resistance note: this thermal data was generated in accordance wit h jedec jesd51 standards. fo r more information, go to www.jedec.org . table 2 functional range parameter symbol values unit note / test condition number min. typ. max. nominal operating voltage v s 534v v s increasing 4.2.1 table 3 thermal resistance 1) 1) not subject to production test, specified by design parameter symbol values unit note / test condition number min. typ. max. thermal resistance - junction to pin5 r thj-pin5 32.0 k/w 4.3.1 thermal resistance - junction to ambient - 1s0p, minimal footprint r thja_1s0p 135.3 k/w 2) 2) specified r thja value is according to jedec jesd 51-3 at natural convection on fr4 1s0p board, footprint; the product (chip+package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 1x 70m cu. 4.3.2 thermal resistance - junction to ambient - 1s0p, 300mm 2 r thja_1s0p_300mm 86.1 k/w 3) 3) specified r thja value is according to jedec jesd51-3 at natural convection on fr4 1s0p board, cu, 300mm 2 ; the product (chip+package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 1x 70m cu. 4.3.3 thermal resistance - junction to ambient - 1s0p, 600mm 2 r thja_1s0p_600mm 75.3 k/w 4) 4) specified r thja value is according to jedec jesd51-3 at natural convection on fr4 1s0p board, 600mm 2 ; the product (chip+package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 1x 70m cu. 4.3.4 thermal resistance - junction to ambient - 2s2p r thja_2s2p 66.8 k/w 5) 5) specified r thja value is according to jedec jesd51-2,-5,-7 at na tural convection on fr4 2s2p board; the product (chip+package) was simulated on a 76.2 x 114.3 x 1.5 mm b oard with 2 inner copper layers (2 x 70m cu, 2 x 35m cu). 4.3.5 thermal resistance - junction to ambient with thermal vias - 2s2p r thja_2s2p 58.4 k/w 6) 6) specified r thja value is according to jedec jesd51-2,-5,-7 at natural convection on fr4 2s2p board with two thermal vias; the product (chip+package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70m cu, 2 x 35m cu. the diameter of the two vias are equal 0.3mm and have a plating of 25um with a copper heatsink area of 3mm x 2mm). jedec51-7: the two plated-through hole vias should have a solder land of no less than 1.25 mm diameter with a drill hole of no less than 0.85 mm diameter. 4.3.6
data sheet 7 rev 1.0, 2012-09-01 ITS4100S-SJ-N electrical characteristics 5 electrical characteristics table 4 v s =13.5v; t j = -40c to 125c;all voltages with respect to ground. currents flowing into the device unless otherwise specified in chapter ?block diagram and terms?. typical values at v s = 13.5v, t j =25c parameter symbol values unit note / test condition number min. typ. max. powerstage nmos on resistance r dson 70 100 m ? i out = 2a; t j = 25c; 9v < v s <34v; v in = 5v 5.0.1 nmos on resistance r dson 140 200 m ? i out = 2a; t j = 125c; 9v < v s <34v; v in = 5v 5.0.2 nominal load current; device on pcb 1) i lnom 2.0 2.4 a t pin5 = 85c 5.0.3 timings of power stages 2) turn on time(to 90% of v out ); l to h transition of v in t on 90 170 s v s =13.5v; r l =47 ? 5.0.4 turn off time (to 10% of v out ); h to l transition of v in t off 90 230 s v s =13.5v; r l =47 ? 5.0.5 on-slew rate (10 to 30% of v out ); l to h transition of v in sr on 0.8 1.7 v / s v s =13.5v; r l =47 ? 5.0.6 off-slew rate; dv out / dt on (70 to 40% of v out ); h to l transition of v in sr off 0.8 1.7 v / s v s =13.5v; r l =47 ? 5.0.7 under voltage lockout (charge pump start-stop-restart) supply undervoltage; charge pump stop voltage v suv 5.5 v v s decreasing 5.0.8 supply startup voltage; charge pump restart voltage v ssu 4.0 5.5 v v s increasing 5.0.9 current consumption operating current i gnd 0.5 1.3 ma v in = 5v 5.0.10 standby current i sstb 10 a v in = 0v; v out = 0v; -40c < t j <85c 5.0.11 standby current i sstb 15 a v in = 0v; v out = 0v; t j =125c 5.0.12 output leakage current i outlk 5a v in = 0v; v out = 0v 5.0.13 protection functions 3) initial peak short circuit current limit i lscp 18 a t j = -40c; v s =20v; v in =5.0v; t m =150as 5.0.14 initial peak short circuit current limit i lscp 10 a t j = 25c ; v s = 20v; v in =5.0v; t m =150as 5.0.15
data sheet 8 rev 1.0, 2012-09-01 ITS4100S-SJ-N electrical characteristics initial peak short circuit current limit i lscp 4a t j =125c ; v s =20v; v in =5.0v; t m =150as 5.0.16 repetitive short circuit current limit t j = t jtrip ; see timing diagrams i lscr 7a v in = 5.0v 5.0.17 output clamp at v out = v s - v dscl (inductive load switch off) v dscl 41 47 v i s = 4ma 5.0.18 overvoltage protection v out = v s - v oncl v saz 41 v i s = 4ma 5.0.19 thermal overload trip temperature t jtrip 150 c 5.0.20 thermal hysteresis t hys 10 k 5.0.21 reverse battery 4) continuous reverse battery voltage v srev - 32 v 5.0.22 forward voltage of the drain-source reverse diode v fds 600 mv i fds =200ma; v in = 0v; t j = 125c 5.0.23 input interface; pin in input turn-on threshold voltage v inon 2.2 v 5.0.24 input turn-off threshold voltage v inoff 0.8 v 5.0.25 input threshold hysteresis v inhys 0.3 v 5.0.26 off state input current i inoff 130a v in = 0.7v 5.0.27 on state input current i inon 130a v in = 5.0v 5.0.28 input resistance r in 1.5 3.5 5.0 k ? 5.0.29 1) device on 50mm x 50mm x 1,5mm epoxy fr4 pcb with 6cm2 (one layer copper 70um thick) copper area for supply voltage connection. pcb in vertical position without blown air. 2) timing values only with high slewrate input signal; otherwise slower. 3) integrated protection functions are designed to prevent ic destruction under fault conditions described in the data sheet. fault conditions are considered as ?outside? normal operating range. protection functions are not designed for continuous repetitive operation. 4) requires a 150w resistor in gnd connecti on. the reverse load current trough the in trinsic drain-source diode of the power- mos has to be limited by the connected load. power dissipation is higher compared to normal operation due to the votage drop across the drain-source diode. the te mperature protection is not functional during reverse current operation! input current has to be limited (see max ratings). table 4 v s =13.5v; t j = -40c to 125c;all voltages with respect to ground. currents flowing into the device unless otherwise specified in chapter ?block diagram and terms?. typical values at v s = 13.5v, t j =25c parameter symbol values unit note / test condition number min. typ. max.
data sheet 9 rev 1.0, 2012-09-01 ITS4100S-SJ-N typical performance graphs 6 typical performance graphs typical performanc e characteristics transient thermal impedance z thja versus pulse time t p @ 6cm2 heatsink area transient thermal impedance z thja versus pulse time t p @ min footprint on-resistance r dson versus junction temperature t j on-resistance r dson versus supply voltage v s d = t p / t d = t p / t ?40 ?25 0 25 50 75 100 125 0 20 40 60 80 100 120 140 160 t j [ c] r dson [m ] v s =13.5v 10 15 20 25 30 35 40 0 20 40 60 80 100 120 140 160 180 200 v s [v] r dson [m ] t j =?40 c;i l =0.5a t j =25 c;i l =0.5a t j =125 c;i l =0.5a
data sheet 10 rev 1.0, 2012-09-01 ITS4100S-SJ-N typical performance graphs typical performanc e characteristics switch on time t on versus junction temperature t j switch off time t off versus junction temperature t j on slewrate sr on versus junction temperature t j off slewrate sr off versus junction temperature t j ?40 ?25 0 25 50 75 100 125 0 20 40 60 80 100 120 140 t j [ c] t on [ s] v s =9v;r l =47 v s =13.5v;r l =47 v s =32v;r l =47 ?40 ?25 0 25 50 75 100 125 0 20 40 60 80 100 120 140 160 180 t j [ c] t off [ s] v s =9v;r l =47 v s =32v;r l =47 ?40 ?25 0 25 50 75 100 125 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 t j [ c] dv dt on [ v s ] v s =9v;r l =47 v s =13.5v;r l =47 v s =32v;r l =47 ?40 ?25 0 25 50 75 100 125 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 t j [ c] ? dv dt off [ v s ] v s =9v;r l =47 v s =13.5v;r l =47 v s =32v;r l =47
data sheet 11 rev 1.0, 2012-09-01 ITS4100S-SJ-N typical performance graphs typical performanc e characteristics standby current i sstb versus junction temperature t j output leakage current i outlk versus junction temperature t j initial peak short circuit current limt i lscp versus junction temperaturetj initial short circuit shutdown time t scoff versus junction temperature t j ?40 ?25 0 25 50 75 100 125 0 1 2 3 4 5 6 t j [ c] i sstb [ a] v in =0v;v s =32v ?40 ?25 0 25 50 75 100 125 0 0.5 1 1.5 2 2.5 t j [ c] i outlk [ a] v in =0v;v s =32v ?40 ?25 0 25 50 75 100 125 0 2 4 6 8 10 12 14 t j [ c] i lscp [a] v s =20v ?40 ?25 0 25 50 75 100 125 0 0.5 1 1.5 2 2.5 3 3.5 4 t j [ c] t scoff [ms] v s =20v
data sheet 12 rev 1.0, 2012-09-01 ITS4100S-SJ-N typical performance graphs typical performanc e characteristics input current consumption i in versus junction temperature t j input current consumption i in versus input voltage v in input threshold voltage v inh,l versus junction temperature t j input threshold voltage v inh,l versussupply voltage v s ?40 ?25 0 25 50 75 100 125 0 2 4 6 8 10 12 14 t j [ c] i in [ a] v in 0.7v;v s =13.5v v in =5v;v s =13.5v 0 2 4 6 8 0 20 40 60 80 100 120 140 160 180 200 v in [v] i in [ a] t j =?40..25 c;v s =13.5v t j =125 c;v s =13.5v ?40 ?25 0 25 50 75 100 125 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 t j [ c] v in [v] off;v s =13.5v on;v s =13.5v 5 10 15 20 25 30 35 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 v s [v] v in [v] off;t j =25 c on;t j =25 c
data sheet 13 rev 1.0, 2012-09-01 ITS4100S-SJ-N typical performance graphs typical performanc e characteristics max. allowable load inductance l versus load current i l max. allowable inductive single pulse switch-off energy e as versus load current i l 0.5 1 1.5 2 2.5 0 500 1000 1500 2000 2500 3000 i l [a] l [mh] t jstart =125 c;v s =13.5v;r l =0 0.5 1 1.5 2 0 500 1000 1500 2000 2500 i l [a] eas [mj] t jstart =125 c;v s =13.5v
data sheet 14 rev 1.0, 2012-09-01 ITS4100S-SJ-N application information 7 application information 7.1 application diagram the following information is given as a hint for the implementation of the device only and shall not be regarded as a description or warranty for a certain functi onality, condition or quality of the device. figure 4 application diagram the ITS4100S-SJ-N can be connected directly to a s upply network. it is recommended to place a ceramic capacitor (e.g. c s = 220nf) between supply and gnd to avoid li ne disturbances. wire harness inductors/resistors are sketched in the application circuit above. the complex load (resistive, capacitive or indu ctive) must be connected to the output pin out. a built-in current limit protects the device against destruction. the ITS4100S-SJ-N can be switched on and off with st andard logic ground related logic signal at pin in. in standby mode (in=l) the ITS4100S-SJ-N is deactivated with very low current consumption. the output voltage slope is controlled during on and off tr ansistion to minimize emissions. only a small ceramic capacitor cout=1nf is recommended to attenuate rf noise. in the following chapters the main features, some typical waverforms and the protection behaviour of the ITS4100S-SJ-N is shown. for further details plea se refer to application notes on the infineon homepage. wire harness complex load electronic control unit wire harness gnd1 3 ITS4100S-SJ-N 4 gate control circuit 7 temperature sensor in out vs 6 5 8 bias supervision overvoltage protection esd protection logic current limiter 2 1 nc gnd c s 220nf gnd2 gnd3 c out 1nf
data sheet 15 rev 1.0, 2012-09-01 ITS4100S-SJ-N application information 7.2 special feature description figure 5 special feature description energy stored in the load inductance is given by : e l = i l 2*l/2 while demagnetizing the load inductance the energy dissipated by the power-dmos is: e as = e s + e l ?e r with an approximate solution for r l =0 : e as = ? * l * i l 2 * {(1- v s / (v s -v dscl ) when an inductive load is switched off a current path must be established until the current is sloped down to zero (all energy removed from the inductive load ). for that purpose the series combination z dscl is connected between gate and drain of the power dmos acting as an active clamp . when the device is switched off , the voltage at out turns negative until v dscl is reached. the voltage on the inductive load is the difference between v dscl and v s . if reverse voltage is applied to the device : 1.) current via load resistance rl : i rev1 = (v rev ?v fds ) / r l 2.) current via input pin in and dignostic pin st : i rev2 = i st +i in ~ (v rev ?v cc )/r in +(v rev ?v cc )/r st1,2 current i st must be limited with the extrernal series resistor r sts . both currents will sum up to: i rev = i rev1 + i rev2 if over-voltage is applied to the v s -pin: voltage is limited to v zdsaz ; current can be calculated : i zdsaz = (v s ?v zdsaz ) / r gnd a typical value for rgnd is 150 . in case of esd pulse on the input pin there is in both polarities a peak current i inpeak ~ v esd / r in z l i rev1 i rev2 v rev l l i l v batt v dscl v out l l e r r l e l e batt e load z l v batt v ds v out v dscl i rev v fds drain-source power stage clamper v dscl : energy calculation: supply over voltage: supply reverse voltage: r gnd r gnd v s 3 ITS4100S-SJ-N 1 r in 5-8 gnd 2 4 out nc in zd in i in zd saz zd dscl r outpd v s 3 ITS4100S-SJ-N 1 r in 5-8 gnd 2 4 out nc in zd in i in zd saz zd dscl r outpd v s 3 ITS4100S-SJ-N 1 r in 5-8 gnd 2 4 out nc in zd in i in zd saz zd dscl r outpd r gnd v s 3 ITS4100S-SJ-N 1 r in 5-8 gnd 2 4 out nc in zd in i in zd saz zd dscl r outpd
data sheet 16 rev 1.0, 2012-09-01 ITS4100S-SJ-N application information 7.3 typical application waveforms figure 6 typical application waveforms of the ITS4100S-SJ-N general input output waveforms: v s t 0 i l t 0 off off on v ds v out 90% 0 +v s 10% t off t i l t 0 t on sr on = dv/dt 30% sr off = dv/dt 70% 40% t waveforms switching a resistive load: off off on on waveforms switching a capacitive load: waveforms switching an inducitive load : v out t t 0 i l t 0 ~ v s v out t t 0 i l t 0 ~ v s t v out v dscl i lsc off off on on off off on on t v in l h v in l h v in l h v in l h
data sheet 17 rev 1.0, 2012-09-01 ITS4100S-SJ-N application information 7.4 protection behavior figure 7 protective behaviour of the ITS4100S-SJ-N overtemperature concept: overtemperature behavior: overtemperature toggling normal waveforms turn on into a short circuit : waveforms short circuit during on state : tt off off overloaded out shorted to gnd off normal operation on t jtrip t hys v out t t 0 i l 0 i lscr i lscp t m t scoff shut down by overtemperature and restart by cooling (toggling ) shut down by overtemperature and restart by cooling (toggling ) v out t v in l t 0 i l 0 i lscr t off off on on v out t t 0 t j t t jtrip t hys off t j off t jrestart cooling down heating up device status h v in l h v in l h i peak controlled by the current limit circuit i peak controlled by the current limit circuit
data sheet 19 rev 1.0, 2012-09-01 ITS4100S-SJ-N package outlines and footprint 8 package outlines and footprint figure 8 pg-dso-8 (plastic dual small outlin e package, rohs-compliant) to meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. green products are rohs-compliant (i.e pb- free finish on leads and suitable for pb-fre e soldering according to ipc/jedec j-std-020
data sheet 20 rev 1.0, 2012-09-01 ITS4100S-SJ-N revision history 9 revision history trademarks of infineon technologies ag aurix?, c166?, canpak?, ci pos?, cipurse?, econopac k?, coolmos?, coolset?, corecontrol?, crossav e?, dave?, di-pol?, easypim?, econobridge?, econodual?, econopim?, econopack?, eicedriver?, eupec?, fcos?, hitfet?, hybridpack?, i2rf?, isoface?, isopack?, mipaq?, modstack?, my-d?, novalithic?, optimos?, origa?, powercode?; primarion?, pr imepack?, primestack?, pr o-sil?, profet?, rasic?, reversave?, satric?, si eget?, sindrion?, sipmos?, smartl ewis?, solid flash?, tempfet?, thinq!?, trenchstop?, tricore?. other trademarks advance design system? (ads) of agilent te chnologies, amba?, arm?, multi-ice?, keil?, primecell?, realview?, thumb?, vision? of arm limited, uk. autosar? is licensed by autosar development partnership. bluetooth? of bluetooth sig inc. cat-iq? of dect forum. colossus?, firstgps? of trimble navigation ltd. emv? of emvc o, llc (visa holdings in c.). epcos? of epcos ag. flexgo? of microsoft corp oration. flexray? is licensed by flexray consortium. hyperterminal? of hilgraeve incorporated. iec? of commission electrot echnique internationale. irda? of infrared data association corporation. iso? of international organization for standardization. matlab? of mathworks, inc. maxim? of maxim integrated products, inc. microtec?, nucleus? of mentor graphics corporation. mipi? of mipi allianc e, inc. mips? of mips technologies, inc., u sa. murata? of murata manufacturing co., microwave office? (mwo) of applied wave research inc., omnivision? of omnivision technologies, inc. openwave? openwave systems inc. red hat? red hat, inc. rfmd? rf micro devices, inc. sirius? of si rius satellite radio inc. solaris? of sun microsystems, inc. spansion? of spansion llc ltd. symbian? of symbian software limited. taiyo yuden? of taiyo yuden co. teaklite? of ceva, inc. tektro nix? of tektronix inc. toko? of toko kabushiki kaisha ta. unix? of x/open company limited. verilo g?, palladium? of cadence design systems, inc. vlynq? of texas instruments incorpor ated. vxworks?, wind river? of wind ri ver systems, inc. zetex? of diodes zetex limited. last trademarks update 2011-11-11 revision date changes v 1.0 12-09-01 datasheet release
edition 2012-09-01 published by infineon technologies ag 81726 munich, germany ? 2012 infineon technologies ag all rights reserved. legal disclaimer the information given in this docu ment shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, infine on technologies hereby disclaims any and all warranties and liabilities of any kind, including witho ut limitation, warranties of non-infrin gement of intellectua l property rights of any third party. information for further information on technology, delivery terms and conditions and prices, please contact the nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements, components may contain dangerous substances. for information on the types in question, please contact the nearest infineon technologies office. the infineon technologies component descr ibed in this data sheet may be used in life-support devices or systems and/or automotive, aviation and aero space applications or systems only with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life- support automotive, aviation and aerospace device or system or to affect the safety or effectiveness of that device or system. life support devices or syste ms are intended to be implanted in th e human body or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

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